The inventive concepts described herein relate to an error check and correction circuit, method, and a memory device.
A NAND flash memory device may be known as a type of Electrically Erasable and Programmable Read Only Memory (EEPROM). The NAND flash memory device may use a NAND string in which a plurality of memory cells is connected in series, so that it stores data with less chip area.
In the NAND flash memory, a data retention characteristic of a storage element (memory cell) may be reduced according to deterioration of a tunnel oxide film due to iterative overwriting, so that an error rate increases. In particular, as memory cells in the NAND flash memory are scaled down in size, the error rate may increase. Thus, “information data” or raw data may be corrected when error bits are generated by adding an error correcting code (ECC) of redundancy data to the information data to be stored, storing the information data and redundancy data as a data string in a flash memory, and correcting the information data based on the error correcting code of redundancy data upon reading the data. Here, information data or raw data may be understood to be data received by the NAND flash memory from an external device, such as a host, in a data write or data programming operation to be stored in the NAND flash memory, and which subsequently may be supplied by the NAND flash memory to an external device in a data read operation.
For example, Japanese Application Publication No. 2009-100369 discloses a NAND flash memory having an error check and correction circuit (ECC circuit), sometimes also referred to as an error detection and correction circuit. An ECC circuit is a circuit which can identify the presence of one or more errors in a set of data, and then correct the one or more errors, provided that the number of errors in the set of data do not exceed a maximum error correction limit or capability of the ECC circuit. In a Chien search unit of the error check and correction circuit disclosed in the cited reference, a location of a bit of input information (i.e., a location of a bit of data string) may be substituted in an error location search equation, and whether a corresponding bit is erroneous may be detected. At outputting of the data string, information corresponding to addresses ranging from LSB to MSB all may be substituted in the Chien search unit to detect error bits in the data string corresponding to the addresses ranging from the LSB to the MSB. When each bit is erroneous, an error correction circuit may correct a data bit to output the corrected data bit. When an error does not exist, the error correction circuit may output the data bit without correction.
However, in a component disclosed in the cited reference, in the event that a bit, corresponding to any address, of the data string is read, the bit to be read may be output from the error correction circuit and first stored in a buffer memory, and then an address of the bit to be read may be additionally provided to the buffer memory to request the bit to be read. That is, in case of the prior art, the error check and correction circuit may perform error correction on a data bit corresponding to an address until error bit correction on all bits in a data string including the bit to be read is completed. This may mean that data is not read in high speed.